Difference between revisions of "LPC2138"
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Jump to navigationJump to search (New page: OK, LPC2138 is an ARM7TDMI, 512kB flash, 32kB ram from NXP/Philips. I'm doing it from zero, since I plan to write some super cool OS for it. == Memory mapping == {| cellspacing="0" borde...) |
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* user flash mode (from boot code), activated by BL, needs valid program sig and non-forced BL. non re-mapped vectors (== stays in flash, bottom) | * user flash mode (from boot code), activated by BL, needs valid program sig and non-forced BL. non re-mapped vectors (== stays in flash, bottom) | ||
* user ram mode (from program), user program can remap vectors to bottom of SRAM | * user ram mode (from program), user program can remap vectors to bottom of SRAM | ||
| + | |||
| + | The 64-byte block is remapped. So some handlers can fit there. | ||
{| cellspacing="0" border="1" | {| cellspacing="0" border="1" | ||
| Line 48: | Line 50: | ||
|- | |- | ||
|0x14 | |0x14 | ||
| − | | | + | |2's complement of checksum of vectors |
|- | |- | ||
|0x18 | |0x18 | ||
| Line 56: | Line 58: | ||
|FIQ | |FIQ | ||
|} | |} | ||
| + | |||
| + | == after reset == | ||
| + | The 12kB boot block is mapped into 0x7d000. It's also visible at 0x7fff d000. | ||
| + | |||
| + | Bootloader checks for valid checksum of vectors, then hands off control to flash at 0x0, or start serial port shit. | ||
Revision as of 10:01, 24 January 2009
OK, LPC2138 is an ARM7TDMI, 512kB flash, 32kB ram from NXP/Philips.
I'm doing it from zero, since I plan to write some super cool OS for it.
Memory mapping
| 0x0 | flash |
| 0x4000 0000 | sram |
| 0x7fff d000 | boot block |
| 0xe000 0000 | vpb peripherals |
| 0xffe0 0000 | ahb peripherals |
arm exception vector locations
ok, so these fuckers can be remapped:
* boot loader mode (on start up), boot block vectors are mapped here * user flash mode (from boot code), activated by BL, needs valid program sig and non-forced BL. non re-mapped vectors (== stays in flash, bottom) * user ram mode (from program), user program can remap vectors to bottom of SRAM
The 64-byte block is remapped. So some handlers can fit there.
| 0x0 | Reset |
| 0x4 | Undefined Instruction |
| 0x8 | Software Interrupt |
| 0xc | Prefetch Abort |
| 0x10 | Data Abort |
| 0x14 | 2's complement of checksum of vectors |
| 0x18 | IRQ |
| 0x1c | FIQ |
after reset
The 12kB boot block is mapped into 0x7d000. It's also visible at 0x7fff d000.
Bootloader checks for valid checksum of vectors, then hands off control to flash at 0x0, or start serial port shit.
